DSP Robotics Support

Spogg wrote:

tulamide wrote:Am I ignored, or does nobody know?

Definitely ignored.

We need a “I read your post but I know nothing" button!

Does it come with a T-Shirt ?

RJHollins wrote:
Does it come with a T-Shirt ?

[Button pushed :] "I read your post but I know nerrthing" (now I'll await the FS T-Shirt ...)

I confess I speed-read the Intel Words that Tula posted and didn't spot that it was actually so garbled; looks like a serious bit of copying-and-pasting gone wrong. With several "from's", "of the's" and "to's" missing altogether. I assume what they were trying to say was :

The source operand can be an XXM register or a 128-bit memory location. The destination operand is an XMM register. The select operand is an 8-bit immediate:
bits 0 and 1 select the value to be moved from the source operand to the destination operand of the low doubleword of the result,
bits 2 and 3 select the value to be moved from the source operand to the destination operand of the second doubleword of the result,
bits 4 and 5 select the value to be moved from the source operand to the destination operand of the third doubleword of the result,
and bits 6 and 7 select the value to be moved from the source operand to the destination operand of the high doubleword of the result.

Well, at least it's in English now, but is it backwards?

Is all Intel documentation written like this? .. it could easily confuse a stupid person

H

HughBanton wrote:Is all Intel documentation written like this? .. it could easily confuse a stupid person

It did confuse me! Hmm...

martinvicanek wrote:

HughBanton wrote:Is all Intel documentation written like this? .. it could easily confuse a stupid person

It did confuse me! Hmm...

Then there’s no hope for the rest of us.

Spogg wrote:

martinvicanek wrote:

HughBanton wrote:Is all Intel documentation written like this? .. it could easily confuse a stupid person

It did confuse me! Hmm...

Then there’s no hope for the rest of us.

Indeed! If we can't rely on Martin, we will all fail!

Ok, so I went to Intel and found this pdf "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2: Instruction Set Reference, A-Z" (what a title!)

It is the newest I could find. It describes what we are using (shufps) as "128-bit Legacy SSE version". It is much more ordered and sorted and formulated, but it is even more confusing for me. And good luck finding the IMM8 bitmasks! They just refer to it as "provides 4 select controls for each element of the destination"

You will find it on page 1274ff

https://www.intel.com/content/dam/www/p ... 325383.pdf

HughBanton wrote:Is all Intel documentation written like this? .. it could easily confuse a stupid person

Yes. That's not a bug, it's a feature.

(Still better than Unix/Solaris 'man' pages though...)