MyCo wrote:Use a lot more "Sample and Hold" primitives.
The Trigger Tutorial v3 from trogluddite made me fully aware of this. After reading it, my idea was to create a few primitives, implementing a simple realtime scheduler, kind of do_forever loop in graphical format, kind of graphical flowchart, kind of Grafcet, from where you define the sequencing, and no more back trigger propagation. Basing on this I would like to interleave (pipeline) the processing like only allowing the GDI+ to start drawing the lines, when the FFT just got calculated. Honestly speaking, I think this is mandatory in case you are in competion with other software and platforms, more or less deterministic. There should be the beginning of a "deterministic" library, as huge bonus, containing a few primitives towards such direction. What do you think about such idea?
MyCo wrote:Don't put everything that has to be done into the "draw" method of Ruby edits. Instead precalculate the stuff, that stays the same.
I had the exact same idea. I need to check if one can exploit the v.width and v. height coming out of the MGUI primitive that's hooked on the Ruby Draw Component. If this is the case, those two values can act as Green math coefficients. This way Ruby only needs to deal with precomputed data scaled between zero and v.width, and between zero and v.height. When the app asks for zoom factors applied to X or Y, those zoom factors would materialize in Green code. I had another idea which is to determine if the GDI+ is smart enough, detecting when the lines that you ask to plot, are so close that they merge in the same screen pixel, in which case ideally speaking the GDI+ would omit drawing consecutive lines that nobody could see, and replace them by a grand "area plot". Have you checked this yet?
MyCo wrote:Optimization for readability: Make more logical groups. Your top schematic of the "FFT-based Audio Analyzer" is very big. It is realy hard to follow every connection without scrolling. A good practice could be: try to use at max. 30 modules per sub schematic. When there are more, select a logical group of modules and put them into a new module.
Actually I'm thinking redrawing the whole app, into "trenches" that I can stack, possibly using buses. This way the layout doesn't change, being 2 channels (like today), or being 4 or 66 channels (like tomorrow). Is there a performance penalty using buses? What programming style would you advise, for systems needing to process 20 identical channels, like rendering 20 channels on the screen ? Is it possible to multi-instantiate a "trench", creating N channels by only writing a few lines of code? Meanwhile, I'm willing to keep the schematic as flat as possible, avoiding sub-modules, sub-sub-modules, etc. The optimal trade-off depends on the the screen you are using. I'm developing using a 40 inch 1920x1080 screen, and I am test-running using a 15 inch 1280x800 screen. I think we need screens, as big as possible both in pixels count, and in dimensions. Creating and debugging Flowstone schematics using a 50 inch 4K screen : that should be quite standard quite shortly.
By the way, I just created a dedicated thread about the NGX LPC4330-Xplorer you were referring. Last year I bought a few NGX LPC4330-Xplorer boards for evaluation. The issue is the ARM Cortex-M0 used as coprocessor. Last year you could not find commercially available developments systems and debuggers, easy to install, easy to configure, able to program and debug both cores together. I don't know if the situation is better now. Last year, Paul Beckman from DSP Concepts was relying on a LPC4330 for porting AudioWeaver on the Cortex-M4 platform. The DSP Concepts team managed to use the SGPIOs for outputting four emulated I2S lanes for feeding a 8-channel audio DAC. In their implementation, the SGPIO was generating the MCLK, a setup that I don't like. I prefear the Codec having its local quartz, querying the data from the DSP. There are videos on YouTube showing the DSP Concepts implementation. The LPC4330 board was overkill, taking a lot of real estate and needing lots of components for interfacing the external memories. The NGX LPC4330-Xplorer should suffice for most audio applications. Infineon is now coming with an interesting Cortex-M4 portfolio, the XMC4000 series featuring many serial ports able to emulate multiple I2S lanes. The STM32F4 is also good for audio, albeit limited to two I2S making it unsuitable for multichannel audio.
See the new dedicated thread here
http://www.dsprobotics.com/support/viewtopic.php?f=6&t=1547Let's not forget the good (old?) PIC32. Most people don't know that the newest PIC32MX1 and PIC32MX2 feature two I2S ports, bidirectional. Price : about 3 eur. Now that Infineon introduced their own flexible serial ports supporting I2S, Microchip must follow the trend, and expand the PIC32MX1 and PIC32MX2 with new devices featuring up to six synchronous serial ports, each configurable as bidirectional I2S (with no MCLK generation). For ultra-lowcost applications, we have the just arrived Cortex-M0+ which is a downgraded M4 cost-optimized, featuring no I2S, thus you need to fiddle with the Frame-Sync and anyway you cannot go beyond 16-bit audio. Price around one dollar, in volume. A one or two dollar price difference between a M0+, a PIC32 and a M4 can make a huge cost difference, in million sellers consumer products like speaking toys, speaking appliances, wireless audio and car audio. The next step is a chip costing one dollar, equipped with a stereo DAC and some digital audio networking interface, kind of upgraded S/PDIF conveying data and audio altogether. Kind of ARM-Cortex Symphony or SigmaDSP. The day such chip arrives, that will be the end of an era, the DSP56K era and the DSP56K derived products. It won't take long. Microchip acquired SMSC in May 2012 for 939 million dollars for initiating an application-specific microcontroller strategy, highly cost optimized when volumes are high. Surely an ARM Cortex-M0+ appears to be very cheap as generic microcontroller, however if you can buy for essentially the same price a one-chip performing as good and containing all the required interfaces, the choice is obvious. Now comes the question : those SMSC application-specific microcontrollers, what architecture they base on? MIPS, ARM, or something else?
Thanks again
Steph