Clock Accuracy - 10ms?

[martinvicanek]

Todays hardware performance is amazing, isnt it?

[nix]

Yeah man,
FS is sample by sample.
You can get 128k out of it too.

[Nowhk]

Todays hardware performance is amazing, isnt it?

Hahah, I don't mean this. I mean that such code:

Code: Select all

i = i + speed;
i = i&(i<samples);

processed at different clock (44100hz as you noticed) instead of 48Khz, makes huge differents if I use it for read sample from a Read module (as you suggested). Because it increase the speed of the whole process.

It is not a simple "for statement" that try to iterate in the slower time (more CPU you have, more faster it will be). Its a "for" that must iterate in a fixed time (i.e. sync). Am I right?

Yeah man,
FS is sample by sample.
You can get 128k out of it too.

But not every kind of processing inside FS! Ruby code is way more slower.
For what I see, only DSP code get and stay in synch at that speed (and maybe also Assembler code).

[Nowhk]

Anyway I think I'm making some other mistakes:

Immagine.png (39.54 KiB) Viewed 23513 times

Without rely on Graph (I removed it; could be delayed as suggested), every time an integer in INDEX module is outputted, I should immediatly see the current sample of that index changing in the other SAMPLE module.

Instead they are way (waayy) to async. What am I missing dudes? Its somethings like 3/4 seconds delayed. Too heavy...

schematic.fsm

(718 Bytes) Downloaded 905 times

can't figure it out!

I guess that:

when i==0 output => -0.693325
when i==1 output => 0.755871

and so on. Instead it "change" around i=1.78 for example, and the first step is quicker than the others (i=1 happens quickly).

[nix]

Yep- only streams use samples.

I'll have a peek at your schematic over the weekend

[Nowhk]

Yep- only streams use samples.

I'll have a peek at your schematic over the weekend

Wow, thanks! You will make me very happy, because I need to made this kind of stuff for the project Ive in my mind. Stay tuned...

[nix]

hmm-
can I get the whole LFO schematic?

Do you need to use ppq?

ps- when you use .00001 as the counter iter,
it takes very long to count to 1, which is where it will register an integer step in the wave read

[nix]

Hey again Nowhk,
I saw your post at Fruity, so I learnt more about the ppq hack.
Here is the counter I have modified->

schematic_integer.fsm

(1.15 KiB) Downloaded 951 times

So the string array and the counter read the same.
Does that help?
http://imageshack.com/a/img633/1214/qJgkVp.png

[billv]

This might help.
Check the blue section in this modulator. (It's an old 'myco' circuit from way back.)

schematic_bv.fsm

(277.2 KiB) Downloaded 1056 times

[Nowhk]

Hey again Nowhk,
I saw your post at Fruity, so I learnt more about the ppq hack.
Here is the counter I have modified->

schematic_integer.fsm

So the string array and the counter read the same.
Does that help?
http://imageshack.com/a/img633/1214/qJgkVp.png

Uhm, I don't understand your schematic: it's identical to mine! And in fact using "i + .00001" I've the same problem.

This might help.
Check the blue section in this modulator. (It's an old 'myco' circuit from way back.)

schematic_bv.fsm

Uhm, not really The method is the same (stream->read mem->ppq tick->out), but the problem is that the index/output of the stream seems not aligned with the DSP code. I can see the values change, but not at the correct integer time/index